The present invention relates in general to integrated circuits, and in particular to an adaptive driver circuit capable of sensing the amount of capacitive load at its output and adjusts its output drive level to produce a desired output signal slew rate.
In certain applications, an electronic system may require an integrated circuit (IC) to drive other circuitry that present variable capacitive load conditions. For example, in a computer system, a clock driver IC would have to drive varying capacitive loads depending on the size of the memory system implemented. When adding memory to a PC, for example, the same IC must drive a larger capacitive load.
As is known in the art, the slew rate of the driver's output signal is dependent upon its output drive (current) supplied to the capacitive load and the value of the capacitive load, as shown in equation 1: EQU Slew rate=.DELTA.V.sub.c /.DELTA.t=I/C (1)
where
V.sub.c =the capacitive load voltage PA1 t=the rise/fall time PA1 I=the current delivered to the capacitive load PA1 C=the value of the capacitive load
Thus, it can be seen that for small load capacitances and/or large driver currents, the slew rate will be correspondingly higher than for large load capacitances and/or small supplied currents.
In order to accommodate variable capacitive loading conditions as described above, conventional driver circuits typically supply a fixed amount of current assuming the largest capacitive load. The fixed current is that which will drive the largest anticipated capacitive load and still meet the desired slew rate. However, in circumstances in which the capacitive load is smaller, the slew rate will be faster than desired.
A faster than desired slew rate is disadvantageous since the driver can generate a greater number of high frequency harmonics. High frequency harmonics can give rise to electromagnetic interference (EMI), which in some instances may exceed the maximum tolerable EMI specifications. Furthermore, the fixed output drive level will generate output signals having varying slew rates as different memory configurations having different load capacitances are installed. The varying clock slew requires slew rate adjustment circuitry which adds to circuit complexity and cost. Lastly, the conventional driver circuit does not possess the capability of providing slew rate adjustability. It is often desirable to alter the slew rate of the input drive signal to correct for effects caused by preceding circuitry.
What is needed is a driver circuit which is capable of varying its output drive level so that the output signal slew rate can be adjusted as desired.